Processing Units - CPU, GPU, APU, TPU, VPU, FPGA, QPU

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• Neuromorphic Computing Chips
• Architectures
• NVIDIA
• Quantum
• CPUs, GPUs, and Now AI Chips
• Moore’s Law Is Dying. This Brain-Inspired Analogue Chip Is a Glimpse of What’s Next | Shelly Fan
• Artificial Intelligence Is Driving A Silicon Renaissance | Rob Toews - Forbes
• MIT’s Tiny New Brain Chip Aims for AI in Your Pocket | Jason Dorrier - SingularityHub ... Alloying conducting channels for reliable neuromorphic computing | H. Yeon, P. Lin, C. Choi, S. Tan, Y. Park, D. Lee, J. Lee, F. Xu, B. Gao, H. Wu, H. Qian, Y. Nie, S. Kim & J. Kim - Nature Nanotechnology
• NVIDIA Faces a Tough New Rival in Artificial Intelligence Chips | Leo Sun - The Motley Fool

Unit - Heart of AI

Central Processing Unit (CPU), Graphical Process Unit (GPU), Associative Processing Unit (APU), Tensor Processing Unit (TPU), Field Programmable Gate Array (FPGA), Vision Processing Unit (VPU), and Quantum Processing Unit (QPU)

• Deep learning rethink overcomes major obstacle in AI industry; sub-linear deep learning engine" (SLIDE) is first algorithm for training deep neural nets faster on CPUs than GPUs | Rice University

GPU - Graphical Process Unit

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• Graphics Processing Unit (GPU) | Wikipedia

APU - Associative Process Unit

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• Autoassociative memory | Wikipedia
• Content-addressable memory | Wikipedia

TPU - Tensor Processing Unit / AI Chip

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• Google Pixel Phone
• Here are the likely specs of the Google Tensor chip in the Pixel 6 | Mishaal Rahman | XDA
• Tensor Processing Unit (TPU) | Wikipedia
• Google AIY Projects Program
• Baidu unveils Kunlun AI chip for edge and cloud computing | Khari Johnson - VentureBeat
• Google Unveils The New Tensor SoC, The Heart Of The New Pixel 6 Line Of Phones | Patrick Moorhead - Forbes

Google Tensor: the chip still has four A55s for the small cores, but it has two Arm Cortex-X1 CPUs at 2.8 GHz to handle foreground processing duties. For "medium" cores, we get two 2.25 GHz A76 CPUs. (That's A76, not the A78 everyone else is using—these A76s are the "big" CPU cores from last year.) The “Google Silicon” team gives us a tour of the Pixel 6’s Tensor SoC | Ron Amadeo - ARS Technical

FPGA - Field Programmable Gate Array

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• Caffe / Caffe2

VPU - Vision Processing Unit

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• Vision Unit (VPU) | Wikipedia

Neuromorphic Chip

• Neuromorphic Computing

QPU - Quantum Processing Unit

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• List of Quantum Processing Units (QPU) | Wikipedia
• Quantum
• Two-qubit gate: the speediest quantum operation yet | Phys.org
• A Preview of Bristlecone, Google’s New Quantum Processor scaled to a square array of 72 Qubits

Cerebras Wafer-Scale Engine (WSE)

• Cerebras

The Cerebras Wafer-Scale Engine (WSE) is the largest chip ever built. It is the heart of our deep learning system. 56x larger than any other chip, the WSE delivers more compute, more memory, and more communication bandwidth. This enables AI research at previously-impossible speeds and scale.

Summit (supercomputer)

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Summit or OLCF-4 is a supercomputer developed by IBM for use at Oak Ridge National Laboratory, which as of November 2018 is the fastest supercomputer in the world, capable of 200 petaflops. Its current LINPACK is clocked at 148.6 petaflops. As of November 2018, the supercomputer is also the 3rd most energy efficient in the world with a measured power efficiency of 14.668 GFlops/watt. Summit is the first supercomputer to reach exaop (exa operations per second) speed, achieving 1.88 exaops during a genomic analysis and is expected to reach 3.3 exaops using mixed precision calculations.

DESIGN: Design Each one of its 4,608 nodes (9,216 IBM POWER9 CPUs and 27,648 Nvidia Tesla GPUs) has over 600 GB of coherent memory (6×16 = 96 GB HBM2 plus 2×8×32 = 512 GB DDR4 SDRAM) which is addressable by all CPUs and GPUs plus 800 GB of non-volatile RAM that can be used as a burst buffer or as extended memory. The POWER9 CPUs and Volta GPUs are connected using Nvidia's high speed NVLink. This allows for a heterogeneous computing model.[14] To provide a high rate of data throughput, the nodes will be connected in a non-blocking fat-tree topology using a dual-rail Mellanox EDR InfiniBand interconnect for both storage and inter-process communications traffic which delivers both 200Gb/s bandwidth between nodes and in-network computing acceleration for communications frameworks such as MPI and SHMEM/PGAS. Summit (supercomputer) | Wikipedia